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| SRAM Austin Semiconductor, Inc. 32K x 8 SRAM SRAM MEMORY ARRAY FEATURES * * * * * * * * * Access Times: 12, 15, & 20ns Fast output enable (tDOE) for cache applications Low active power: 400 mW (TYP) Low power standby Fully static operation, no clock or refresh required High-performance, low-power CMOS double-metal process Single +5V (+10%) Power Supply Easy memory expansion with CE\ All inputs and outputs are TTL compatible AS5C2568 PIN ASSIGNMENT (Top View) 28-PIN PSOJ (DJ) OPTIONS * Timing 12ns access* 15ns access 20ns access * Package(s)** Plastic SOJ MARKING -12 -15 -20 DJ XT IT No. 906 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCC 27 WE\ 26 A13 25 A8 24 A9 23 A11 22 OE\ 21 A10 20 CE\ 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 * Operating Temperature Ranges Military -55oC to +125oC Industrial -40oC to +85oC * -12 available in IT only. ** For ceramic version of this product, see the MT5C2568 data sheet. GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs using a four-transistor memory cell. These SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. For more products and information please visit our web site at www.austinsemiconductor.com AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM A0 Vcc AS5C2568 DECODER 256 x 1024 MEMORY ARRAY GND A14 I/O0 I/O DATA CIRCUIT I/O7 COLUMN I/O 9A128-1 CE\ OE\ CONTROL CIRCUIT WE\ TRUTH TABLE MODE STANDBY READ READ WRITE OE\ X L H X CE\ H L L L WE\ X H H L DQ HIGH-Z Q HIGH-Z D POWER STANDBY ACTIVE ACTIVE ACTIVE AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Input or DQ Relative to Vss..................................................................-0.5V to Vcc +0.5V Voltage on Vcc Supply Relative to Vss.......................-1V to +7V Storage Temperature..............................................-65oC to +150oC Power Dissipation.......................................................................1W Short Circuit Output Current............................................20mA Lead Temperature (soldering 10 seconds)........................+260oC Max. Junction Temperature.................................................+175oC AS5C2568 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC or -40oC to +85oC; VCC = 5.0V +10%) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage 0V ! , ) *+ ) - $%&' . /*01 ( ' ) *+ $%&' ( ' ) *+ "# 2 $%&' ( 3 2 & ' 4 ' 5 ' ) *+ , ) *+ ) - . /*01 , ) 67 * $%4'89'( ' ) *+ ' &'22:9' ' 4' 89'( , ) 67 CAPACITANCE PARAMETER Input Capacitance Output Capacitance AS5C2568 Rev. 2.6 06/05 CONDITIONS TA = 25 C, f = 1MHz Vcc = 5V o SYM CIN CIO 3 MAX 11 11 UNITS pF pF NOTES 4 4 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SRAM Austin Semiconductor, Inc. AS5C2568 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55oC < TC < 125oC or -40oC to +85oC; VCC = 5.0V +10%) DESCRIPTION READ CYCLE READ cycle time Address access time Chip enable access time Output hold from address change Chip enable to output in Low-Z Chip disable to output in High-Z Chip enable to power-up time Chip disable to power-down time Output enable to access time Output enable to output in Low-Z Output disable to output in High-Z WRITE CYCLE WRITE cycle time Chip enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write enable to output in High-Z tWC tCW tAW tAS tAH tWP tDS tDH tLZWE tHZWE 12 9 9 0 0 10 7 0 2 0 7 15 10 10 0 0 12 8 0 2 0 7 20 12 12 0 0 15 10 0 2 0 9 ns ns ns ns ns ns ns ns ns ns 7 6, 7 tRC tAA tACE tOH tLZCE tHZCE tPU tPD tAOE tLZOE tHZOE 0 6 0 12 6 0 7 2 2 7 0 15 7 0 8 12 12 12 2 2 8 0 20 8 15 15 15 2 2 9 20 20 20 ns ns ns ns ns ns ns ns ns ns ns 6 7 6, 7 4 4 SYM -12 MIN MAX -15 MIN MAX -20 MIN MAX UNITS NOTES AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM Austin Semiconductor, Inc. AC TEST CONDITIONS Input pulse levels....................................................Vss to 3V Input rise and fall times.....................................................5ns Input timing reference level.............................................1.5V Output reference level......................................................1.5V Output load.................................................See figures 1 & 2 +5V 480 Q 255 30 pF Q 255 Fig. 2 OUTPUT LOAD EQUIVALENT 5 pF AS5C2568 +5V 480 NOTES 1. 2. 3. All voltages referenced to VSS (GND). -3V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f= 1 Hz. t RC (MIN) This parameter is guaranteed but not tested. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured 500mV typical from steady state voltage, allowing for actual tester RC time constant. 7. Fig. 1 OUTPUT LOAD EQUIVALENT 4. 5. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION VCC for Retention Data CE\ > (VCC-0.2V) Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VIN > (VCC-0.2V) or < 0.2V ICCDR 1 mA CONDITIONS SYM VDR MIN 2 MAX UNITS V NOTES tCDR tR 0 tRC -- ns ns 4 4, 11 LOW Vcc DATA RETENTION WAVEFORM VCC t DATA RETENTION MODE 4.5V CDR V DR VDR > 2V 4.5V t R AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 432 4321 4321 1 4321 321 321 321 321 CE\ VIH VIL 4215 3325 876 42114321 33214321 832 42114321 32114321 876 3325 4765 876 87654321 321 21 87654321 87654321 87654321 DON'T CARE UNDEFINED SRAM Austin Semiconductor, Inc. AS5C2568 READ CYCLE NO. 1 tRC ADDRESS tAA tOH DQ PREVIOUS DATA VALID VALID 8, 9 DATA VALID READ CYCLE NO. 2 tRC CE\ tAOE 7, 8, 10, 12 tHZOE tLZOE OE\ tLZCE tACE DQ tPU tPD Icc DATA VALID tHZCE AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 321 321 321 4321 1 4321 4321 432 DON'T CARE UNDEFINED SRAM Austin Semiconductor, Inc. WRITE CYCLE NO. 1 12 (Chip Enabled Controlled) tWC ADDRESS tAW tAH tAS CE\ tWP1 WE\ tDS D Q HIGH Z DATA VAILD AS5C2568 tCW tDH WRITE CYCLE NO. 2 7, 12 (Write Enabled Controlled) tWC ADDRESS tAW tAH tCW CE\ tAS tWP1 WE\ tDH D Q HIGH-Z DATA VALID NOTE: Output enable (OE\) is inactive (HIGH). AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 321 321 321 DON'T CARE 432 4321 4321 1 4321 UNDEFINED SRAM Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #906 (Package Designator DJ) E E1 AS5C2568 A A1 R D E2 L e b SYMBOL A A1 A2 B b C D E E1 E2 e ASI SPECIFICATIONS MIN MAX 0.128 0.148 0.025 --0.082 --0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC * All measurements are in inches. AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM Austin Semiconductor, Inc. AS5C2568 ORDERING INFORMATION EXAMPLE: AS5C2568DJ-15/IT Device Number AS5C2568 AS5C2568 AS5C2568 Package Speed ns Process Type DJ -12 /* DJ -15 /* DJ -20 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing 12ns offered in IT only -40oC to +85oC -55oC to +125oC -55oC to +125oC AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 |
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